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68020 FEATURES
Selection of Processor Speeds: 16.67, 20, 25 MHz Military Temperature Range: -55C to +125C Packaging * 114 pin Ceramic PGA (P2) * 132 lead Ceramic Quad Flatpack, CQFP (Q2) Object-code compatible with earlier 68000 Microprocessors Addressing mode extensions for enhanced support of high-level languages Bit Field Data Type Accelerates Bit-Oriented Applications-i.e., Video Graphics Fast On-Chip Instruction Cache Speeds Instructions and Improves Bus Bandwidth Coprocessor Interface to Companion 32-Bit Peripherals-the 68881 and 68882 Floating-Point Coprocessors and the 68851 Paged Memory Management Unit Pipelined Architecture with High Degree of Internal Parallelism allowing Multiple Instructions to be executed concurrently
WC32P020-XXM
High-Performance Asynchronous Bus Is Nonmultiplexed and Full 32-Bits Dynamic Bus Sizing Efficiently Supports 8-/16-/32Bit Memories and Peripherals Full Support of Virtual Memory and Virtual Machine 16 32-Bit General-Purpose Data and Address Registers Two 32-Bit Supervisor Stack Pointers and Five Special-Purpose Control Registers 18 Addressing Modes and 7 Data Types 4 GigaByte Direct Addressing Range
DESCRIPTION
The WC32P020 is a 32-bit implementation of the 68000 Family of microprocessors. Using HCMOS technology, the WC32P020 is implemented with 32-bit registers and data paths, 32-bit addresses, a powerful instruction set, and flexible addressing modes.
FIGURE 1 - BLOCK DIAGRAM
MICRO MACHINE SEQUENCER MICROROM NANOROM INSTRUCTION DECODE
CONTROL SECTION
INSTRUCTION PIPE
TAG CACHE
EXECUTION UNIT INSTRUCTION OPERAND DATA ADDRESS ADDRESS SECTION SECTION SECTION
INSTRUCTION CACHE
ADDRESS PADS
BUS CONTROLLER
DATA PADS BUS CONTROLLER
White Electronic Designs Corp. reserves the right to change products or specifications without notice. December 2002 Rev. 2 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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WC32P020-XXM
FIGURE 2 - PIN CONFIGURATION FOR WC32P020-XXM, CQFP (Q2) TOP VIEW
NC BGAC# BR# A0 A1 A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 VCC VCC GND GND A16 A15 A14 A13 A12 A11 A10 NC NC 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117
116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84
NC NC GND BG# VCC GND GND CLK RESET# VCC VCC RMC FC0 FC1 FC2 SIZ0 SIZ1 DBEN# ECS# CDIS# AVEC# DSACK0# DSACK1# BERR# GND GND HALT AS# DS# GND GND R/W# NC
NC D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 GND GND VCC VCC D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 NC NC
FIGURE 3 - PIN CONFIGURATION FOR WC32P020-XXM, PGA (P2)
N
D31 D28 D29 R/W# HALT# D25 D26 D30 GND GND D22 D24 D27 D20 D21 D23 D17 D18 D19 GND D16 GND VCC VCC D15 D14 D13 D11 D12 D10 D7 D9 D6 GND D8 D5 D3 D1 IPL0# IPL2# VCC GND GND A2 A4 A0 A30 A28 A29 A27 A26 A25 A24 A23 A21 A20 A22 A17 A18 A19 A16 GND VCC A12 D15 GND A9 D13 A14 A7 A10 A11 VCC D4 D2 D0 IPL1# GND VCC IPEND# OCS# A3 A5 A6 A8
M
DS#
L
AS#
K
GND
J
DSACK1# BERR#
H
CDIS# AVEC# DSACK0# SIZ1 FC2 RMC# VCC CLK BG# A1 DBEN# FC1 VCC VCC GND BR# A31
G
ECS#
F
SIZ0
E
FC0
D
VCC
C
RESET#
B
GND
A
BGACK#
1
2
NC NC NC A9 A8 A7 A6 A5 A4 A3 A2 GND OSC# IPEND# VCC VCC GND GND IPL2# IPL1# IPL0# D0 D1 D2 D3 D4 GND GND VCC VCC D5 NC NC
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
3
4
5
6
7
8
9
10
11
12
13
White Electronic Designs Corp. reserves the right to change products or specifications without notice. December 2002 Rev. 2 2 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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ADDRESSING MODES
Addressing Register Direct Data Register Direct Address Register Direct Register Indirect Address Register Indirect Address Register Indirect with Postincrement Address Register Indirect with Predecrement Address Register Indirect with Displacement Register Indirect with Index Address Register Indirect with Index (8-Bit Displacement) Address Register Indirect with Index (Base Displacement) Memory Indirect Memory Indirect Postindexed Memory Indirect Preindexed Program Counter Indirect with Displacement Program Counter Indirect with Index PC Indirect with Index (8-Bit Displacement) PC Indirect with Index (Base Displacement) Program Counter Memory Indirect PC Memory Indirect Postindexed PC Memory Indirect Preindexed Absolute Absolute Short Absolute Long Immediate Syntax Dn An (An) (An) + - (An) (d16,An) (d8,An,Xn) (bd,An,Xn) ([bd,An],Xn,od) ([bd,An,Xn],od) (d16,PC) (d8,PC,Xn) (bd,PC,Xn) ([bd,PC],Xn,od) ([bd,PC,Xn],od) ( xxx).W (xxx).L #(data)
WC32P020-XXM
NOTES: Dn = Data Register, DO-D7 An = Address Register, AO-A7 d8, d16 = A twos-complement or sign-extended displacement; added as part of the effective address calculation; size is 8 (d8) or 16 (d16) bits; when omitted, assemblers use a value of zero. Xn = Address or data register used as an index register; form is Xn.SIZE*SCALE, where SIZE is.W or .L (indicates index register size) and SCALE is 1, 2, 4, or 8 (index register is multiplied by SCALE); use of SIZE and/or SCALE is optional. bd = A twos-complement base displacement; when present, size can be 16 or 32 bits. od = 0uter displacement, added as part of effective address calculation after any memory indirection, use is optional with a size of 16 or 32 bits. PC = Program Counter (data) = Immediate value of 8, 16, or 32 bits ( ) = Effective Address [ ] = Use as indirect access to long-word address.
INSTRUCTION SET
Mnemonic ABCD ADD ADDA ADDI ADDQ ADDX AND ANDI ASL, ASR Description Add Decimal with Extend Add Add Address Add Immediate Add Quick Add with Extend Logical AND Logical AND Immediate Arithmetic Shift Left and Right
Mnemonic Bcc BCHG BCLR BFCHG BFCLR BFEXTS BFEXTU BFFFO BFINS BFSET BFTST BKPT BRA BSET BSR BTST CALLM CAS CAS2 CHK CHK2 CLR CMP CMPA CMPI CMPM CMP2 DBcc DIVS, DIVSL DIVU, DIVUL EOR EORI EXG EXT, EXTB ILLEGAL JMP JSR LEA LINK LSL, LSR MOVE MOVEA MOVE CCR MOVE SR MOVE USP MOVEC MOVEM MOVEP MOVEQ MOVES MULS MULU
Description Branch Conditionally Test Bit and Change Test Bit and Clear Test Bit Field and Change Test Bit Field and Clear Signed Bit Field Extract Unsigned Bit Field Extract Bit Field Find First One Bit Field Insert Test Bit Field and Set Test Bit Field Breakpoint Branch Test Bit and Set Branch to Subroutine Test Bit Call Module Compare and Swap Operands Compare and Swap Dual Operands Check Register Against Bound Check Register Against Upper and Lower Bounds Clear Compare Compare Address Compare Immediate Compare Memory to Memory Compare Register Against Upper and Lower Bounds Test Condition, Decrement and Branch Signed Divide Unsigned Divide Logical Exclusive OR Logical Exclusive OR Immediate Exchange Registers Sign Extend Take Illegal Instruction Trap Jump Jump to Subroutine Load Effective Address Link and Allocate Logical Shift Left and Right Move Move Address Move Condition Code Register Move Status Register Move User Stack Pointer Move Control Register Move Multiple Registers Move Peripheral Move Quick Move Alternate Address Space Signed Multiply Unsigned Multiple
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INSTRUCTION SET (cont'd)
Mnemonic NBCD NEG NEGX NOP NOT OR ORI ORI CCR ORI SR PACK PEA RESET ROL, ROR ROXL, ROXR RTD RTE RTM RTR RTS SBCD Scc STOP SUB SUBA SUBI SUBQ SUBX SWAP TAS TRAP TRAPcc TRAPV TST UNLK UNPK Description Negate Decimal with Extend Negate Negate with Extend No Operation Logical Complement Logical Inclusive OR Logical Inclusive OR Immediate Logical Inclusive OR Immediate to Condition Codes Logical Inclusive OR Immediate to Status Register Pack BCD Push Effective Address Reset External Devices Rotate Left and Right Rotate with Extend Left and Right Return and Deallocate Return from Exception Return from Module Return and Restore Codes Return from Subroutine Subtract Decimal with Extend Set Conditionally Stop Subtract Subtract Address Subtract Immediate Subtract Quick Subtract with Extend Swap Register Words Test Operand and Set Trap Trap Conditionally Trap on Overflow Test Operand Unlink Unpack BCD
WC32P020-XXM
SIGNAL DESCRIPTION
The VCC and GND pins are separated into four groups to provide individual power supply connections for the address bus buffers, data bus buffers, and all other buffers and internal logic. See FIGURE 4.
Group Address Bus Data Bus Logic Clock
VCC A9, D3 M8, N8, N13 D1, D2, E3, G11, G13 --
GND A10, B9, C3, F12 L7, L11, N7, K3 G12, H13, J3, K1 B1
FIGURE 4 - FUNCTIONAL SIGNAL GROUPS
FUNCTION CODES ADDRESS BUS DATA BUS
FC0-FC2 A0-A31 D0-D31
CDIS# INTERRUPT PRIORITY
CACHE CONTROL
IPL0#-IPL2# IPEND# AVEC# SIZ0 SIZ1 INTERRUPT CONTROL
TRANSFER SIZE
BR# BG# BGACK# RESET# HALT# BERR# CLK Vcc (10) GND (13)
BUS ARBITRATION CONTROL
COPROCESSOR INSTRUCTIONS
Mnemonic cpBcc cpDBcc cpGEN Mnemonic cpRESTORE cpSAVE cpScc cpTRAPcc Description Branch Conditionally Test Coprocessor Condition, Decrement and Branch Coprocessor General Instruction Description Restore Internal State of Coprocessor Save Internal State of Coprocessor Set Conditionally Trap Conditionally
ASYNCHRONOUS BUS CONTROL
ECS# OCS# RMC# AS# DS# R/W# DBEN# DSACK0# DSACK1#
BUS EXCEPTION CONTROL
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SIGNAL INDEX
Signal Name Function Codes Address Bus Data Bus Size External Cycle Start Operand Cycle Start Read,Write Read-Modify-Write Cycle Address Strobe Data Strobe Data Buffer Enable Data Transfer and Size Acknowledge Interrupt Priority Level Interrupt Pending Autovector Bus Request Bus Grant Bus Grant Acknowledge Reset Halt Bus Error Cache Disable Clock Power Supply Ground Mnemonic FC2-FC0 A0-A31 D0-D31 SIZ0/SIZ1 ECS# OCS# R/W# RMC# AS# DS# DBEN# DSACK0#/DSACK1# Function
WC32P020-XXM
3-bit function code used to identify the address space of each bus cycle. 32-bit address bus. 32-bit data bus used to transfer 8, 16, 24, or 32 bits of data per bus cycle. Indicates the number of bytes remaining to be transferred for this cycle. These signals, together with A1 and A0, define the active sections of the data bus. Provides an indication that a bus cycle is beginning. Identical operation to that of ECS except that OCS is asserted only during the first bus cycle of an operand transfer. Defines the bus transfer as a processor read or write. Provides an indicator that the current bus cycle is part of an indivisible read-modify-write operation. Indicates that a valid address is on the bus. Indicates that valid data is to be placed on the data bus by an external device or has been placed on the data bus by the WC32P020-XXM. Provides an enable signal for external data buffers. Bus response signals that indicate the requested data transfer operation has completed. In addition, these two lines indicate the size of the external bus port on a cycle-by-cycle basis and are used for asynchronous transfers. Provides an encoded interrupt level to the processor. Indicates that an interrupt is pending. Requests an autovector during an interrupt acknowledge cycle. Indicates that an external device requires bus mastership. Indicates that an external device may assume bus mastership. Indicates that an external device has assumed bus mastership. System reset. Indicates that the processor should suspend bus activity. Indicates that an erroneous bus operation is being attempted. Dynamically disables the on-chip cache to assist emulator support Clock input to the processor. Power supply. Ground connection.
IPL0#-IPL2# IPEND# AVEC# BR# BG# BGACK# RESET# HALT# BERR# CDIS# CLK Vcc GND
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MAXIMUM RATINGS
Symbol VCC VI PDMAX TCASE TCASE TSTG Parameter Supply voltage Input voltage Max Power dissipation Operating temperature (Mil.) Operating temperature (Ind.) Storage temperature -55 -40 -55 Min -0.3 -0.3 Max +7.0 +7.0 2.0 +125 +85 +150 Unit V V W C C C
WC32P020-XXM
Thermal Characteristics
(with no heat sink or airflow) Characteristic Thermal Resistance -- Junction to Ambient PGA Package CQFP Package Thermal Resistance -- Junction to Case PGA Package CQFP Package Symbol Value JA 26 46 JC 3 15 C/W Rating C/W
TJ
Junction temperature
+160
C
POWER CONSIDERATIONS
The average chip junction temperature, TJ, in C can be obtained from: TJ = TA + (PD * JA) where: TA = Ambient Temperature, C qJA = Package Thermal Resistance, Junction-toAmbient, C/W PD = PINT+PI/O PINT = ICC x VCC, Watts-Chip Internal Power PI/O = Power Dissipation on Input and Output Pins-User Determined For most applications, PI/O < PlNT and can be neglected. The following is an approximate relationship between PD and TJ (if PI/O is neglected ): PD = K(TJ + 273C) Solving equations (1) and (2) for K gives: K = PD * (TA + 273C) + qJA * PD2 (3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. The total thermal resistance of a package (JA) can be separated into two components, JC and CA, representing the barrier to heat flow from the semiconductor junction to the package (case) surface (JC) and from the case to the outside ambient (qCA). These terms are related by the equation: JA = JC + CA (4) (2) (1) JC is device related and cannot be influenced by the user. However, CA is user dependent and can be minimized by such thermal management techniques as heat sinks, ambient air cooling, and thermal convection. Thus, good thermal management on the part of the user can significantly reduce CA so that JA approximately equals JC. Substitution of JC for JA in equation (1) will result in a lower semiconductor junction temperature.
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DC ELECTRICAL CHARACTERISTICS
VCC = 5.0 VDC 5%, GND = 0 VDC, -55C TA +125C Characteristics Input High Voltage Input Low Voltage Input Leakage Current GND - VIN - VCC High-Z (Off State) Leakage Current Output High Voltage Output Low Voltage IOL = 3.2 mA IOL = 5.3 mA IOL = 2.0 mA IOL = 10.7 mA Maximum Supply Current Capacitance (1) VIN = 0V, TA = 25C, f = 1MHz Load Capacitance
NOTES: 1. Capacitance is guaranteed by design but not tested.
WC32P020-XXM
Symbol VIH VIL
Min 2.0 GND -0.5 -4 -20
Max VCC 0.8 4.0 20 20 --
Unit V V A
BERR#, BR#, BGACK#, CLK, IPL0-2#, AVEC#, CDIS#, DSACK0#, DSACK1# HALT#, RESET# A31-0, AS#, DBEN#, DS#, D31-0, FC2-0 R/W#, RM#, SIZ1-0 A31-0, AS#, BG#, D31-0, DBEN#, DS#, ECS#, R/W#, IPEND#, OCS#, RMC#, SIZ1-0, FC2-0 A31-0, FC2-0, SIZ1-0, BG#, D31-0 AS#, DS#, R/W#, RMC#, DBEN#, IPEND# ECS#, OCS# HALT#, RESET#
IIN
ITSI VOH VOL
-20 2.4
A V V
-- -- -- -- ICC CIN -- -- --
0.5 0.5 0.5 0.5 333 20 50 130 mA pF pF
ECS#, OCS# All Other
CL
AC ELECTRICAL SPECIFICATIONS - CLOCK INPUT (see Figure 5)
Characteristic Frequency of Operation Cycle Time Clock Pulse Width Rise and Fall Times Specification 1 2,3 4,5 16.67 MHz Min Max 8 16.67 60 125 24 95 -- 5 20 MHz Min 12.5 50 20 -- Max 20 80 54 5 Min 12.5 40 19 -- 25MHz Max 25 80 61 4 Unit MHz ns ns ns
FIGURE 5 - CLOCK INPUT TIMING DIAGRAM
1 2
2.0 V 0.8 V
3
4
5
NOTE: Timing measurements are referenced to and from a low 0.8V and a high voltage of 2.0V, unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0.8V and 2.0V.
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VCC = 5.0 VDC 5%, GND = 0 VDC, -55C TA +125C 16.67 MHz Characteristic Specification Clock high to Address, FC, Size, RMC# Valid 6 Clock High to ECS#, OCS# Asserted 6A Clock High to Address, Data, FC, Size, RMC#, High Impedance 7 Clock high to Address, FC, Size, RMC# Invalid 8 Clock Low to AS#, DS# Asserted 9 AS# to DS# Assertion (Read) (Skew) 9A (1) AS# Asserted to DS# Asserted (Write) 9B (11) ECS# Width Asserted 10 OCS# Width Asserted 10 ECS#, OCS# width Negated 10B (7) Address, FC, Size, RMC#, Valid to AS# (and DS# Asserted Read) 11 Clock Low to AS#, DS# Negated 12 Clock Low to ECS#, OCS# Negated 12A AS#, DS# Negated to Address, FC, Size, RMC# Invalid 13 AS# (and DS# Read) Width Asserted 14 DS# Width Asserted Write 14A AS#, DS# Width Negated 15 DS# Negated to AS# Asserted 15A (8) Clock High to AS#, DS#, R/W# Invalid, High Impedance 16 AS#, DS# Negated to R/W# Invalid 17 Clock High to R/W# High 18 Clock High to R/W# Low 20 R/W# High to AS# Asserted 21 R/W# Low to DS# Asserted (Write) 22 Clock High to Data Out Valid 23 DS# Negated to Data Out Invalid 25 DS# Negated to DBEN# Negated (Write) 25A (9) Data Out Valid to DS# Asserted (Write) 26 Data-In Valid to Clock Low (Data Setup) 27 Late BERR#/HALT# Asserted to Clock Low Setup Time 27A AS#, DS# Negated to DSACKx#, BERR#, HALT#, AVEC# Negated 28 DS# Negated to Data-In Invalid (Data-In Hold Time) 29 DS# Negated to Data-In (High Impedance) 29A DSACKx# Asserted to Data-In Valid 31 (2) DSACKx# Asserted to DSACKx# Valid (DSACK# Asserted Skew) 31A (3) RESET# Input Transition Time 32 Clock Low to BG# Asserted 33 Clock Low to BG# Negated 34 BR# Asserted to BG# Asserted (RMC# Not Asserted) 35 BGACK# Asserted to BG# Negated 37 Min 0 0 0 0 1 -15 37 20 20 15 15 0 0 15 100 40 40 35 -- 15 0 0 15 75 -- 15 15 15 5 20 0 0 -- -- -- -- 0 0 1.5 1.5 Max 30 20 60 -- 30 15 -- -- -- -- -- 30 30 -- -- -- -- -- 60 -- 30 30 -- -- 30 -- -- -- -- -- 80 -- 60 50 15 1.5 30 30 3.5 3.5 20 MHz Min 0 0 0 0 1 -10 32 15 15 10 10 0 0 10 85 38 38 30 -- 10 0 0 10 60 -- 10 10 10 5 15 0 0 -- -- -- -- 0 0 1.5 1.5
WC32P020-XXM
AC ELECTRICAL SPECIFICATIONS - READ AND WRITE CYCLES
25 MHz Min 0 0 0 0 1 -10 27 15 15 5 6 0 0 10 70 30 30 25 -- 10 0 0 5 50 -- 5 5 5 5 10 0 0 -- -- -- -- 0 0 1.5 1.5 Max 25 12 40 -- 18 10 -- -- -- -- -- 15 15 -- -- -- -- -- 40 -- 20 20 -- -- 25 -- -- -- -- -- 50 -- 40 32 10 1.5 20 20 3.5 3.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Clks ns ns Clks Clks
Max 25 15 50 -- 25 10 -- -- -- -- -- 25 25 -- -- -- -- -- 50 -- 25 25 -- -- 25 -- -- -- -- -- 65 -- 50 43 10 1.5 25 25 3.5 3.5
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Characteristic Specification 16.67 MHz Min BGACK# Asserted to BR# Negated BG Width Negated BG# Width Asserted Clock High to DBEN# Asserted (Read) Clock High to DBEN# Negated (Read) Clock High to DBEN# Asserted (Write) Clock High to DBEN# Negated (Write) R/W# Low to DBEN# Asserted (Write) DBEN# Width Asserted Read Write R/W# Width Valid (Write or Read) Asynchronous Input Setup Time Asynchronous Input Hold Time DSACKx# Asserted to BERR#, HALT# Asserted Data Out Hold from Clock High R/W# Valid to Data Bus Impedance Change RESET# Pulse Width (Reset Instruction) BERR# Negated to HALT# Negated (Rerun) BGACK# Negated to Bus Driven BG# Negated to Bus Driven 46 47A 47B 48 (4) 53 55 56 57 58 (10) 59 (10) 37A (6) 39 39A 40 41 42 43 44 45 (5) 0 90 90 0 0 0 0 15 60 120 150 5 15 - 0 30 512 0 1 1 Max 1.5 - - 30 30 30 30 - - - - - - 30 - - - - - - Min 0 75 75 0 0 0 0 10 50 100 125 5 15 - 0 25 512 0 1 1 20 MHz Max 1.5 - - 25 25 25 25 - - - - - - 20 - - - - - -
WC32P020-XXM
AC ELECTRICAL SPECIFICATIONS - READ AND WRITE CYCLES (CONT'D)
25MHz Min 0 60 60 0 0 0 0 10 40 80 100 5 10 - 0 20 512 0 1 1 Max 1.5 - - 20 20 20 20 - - - - - - 18 - - - - - - ns ns ns ns ns ns Clks ns Clks Clks Clks ns ns ns ns ns ns ns ns Unit
NOTES: 1. This number can be reduced to 5ns if strobes have equal loads. 2. If the asynchronous setup time (#47A) requirements are satisfied, the DSACKx# low data setup time (#31) and DSACKx# low to BERR# low setup time (#48) can be ignored. The data must only satisfy the data-in to clock low setup time (#27) for the following clock cycle, and BERR# must only satisfy the late BERR low to clock low setup time (#27A) for the following clock cycle. 3. This parameter specifies the maximum allowable skew between DSACK0# to DSACK1# asserted or DSACK1# to DSACK0# asserted; specification #47A must be met by DSACK0# or DSACK1#. 4. This specification applies to the first (DSACK0# or DSACK1#) DSACKx# signal asserted. In the absence of DSACKx#, BERR# is an asynchronous input setup time (347A). 5. DBEN# may stay asserted on consecutive write cycles. 6. The minimum values must be met to guarantee proper operation. If this maximum value is exceeded, BG may be reasserted.
7. This specification indicates the minimum high time for ECS# and OCS# in the event of an internal cache hit followed immediately by a cache miss or operand cycle. 8. This specification guarantees operation with the 68881/68882, which specifies a minimum time for DS# negated to AS# asserted. Without this specification, incorrect interpretation of specifications #9A and #15 would indicate that the WC32P020-XXM does not meet the 68881/68882 requirements. 9. This specification allows a system designer to guarantee data hold times on the output side of data buffers that have output enable signals generated with DBEN#. 10. These specifications allow system designers to guarantee that an alternate bus master has stopped driving the bus when the 68020 regains control of the bus after an arbitration sequence. 11. This specification allows system designers to qualify the CS# signal of an 68881/68882 with AS# (allowing 7 ns for a gate delay) and still meet the CS# to DS# setup time requirement.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. December 2002 Rev. 2 9 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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FIGURE 6 - READ CYCLE TIMING DIAGRAM
WC32P020-XXM
S0 CLK 6 A31-A0
S1
S2
S3
S4
S5
7
FC2-FC0
SIZE 12A 10 ECS# 6A OCS# 10A 9A AS# 11 DS# 18 R/W# 21 DSACK0# 31A DSACK1# 31 D31-D0 27 DBEN# 45 BERR# 40 41 27A HALT# 48 ALL ASYNCHRONOUS INPUTS 47A 47B 29 29A 28 9 46 17 20 12 14 13 16 8
NOTE: Timing measurements are referenced to and from a low 0.8V and a high voltage of 2.0V, unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0.8V and 2.0V.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. December 2002 Rev. 2 10 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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FIGURE 7 - WRITE CYCLE TIMING DIAGRAM
S0 S1 CLK 6 A31-A0 7 S2 S3 S4 S5
WC32P020-XXM
FC2-FC0 10 SIZE 12A ECS# 6A OCS# 10A 11 AS# 9 DS# 14A 20 22 R/W# 9 46 DSACK0# 31A DSACK1# 55 23 D31-D0 44 DBEN# 45 BERR# 42 48 HALT# 27A
NOTE: Timing measurements are referenced to and from a low 0.8V and a high voltage of 2.0V, unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0.8V and 2.0V.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. December 2002 Rev. 2 11 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
8
13 14 15
12
17
28
53
26
25
43
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FIGURE 8 - BUS ARBITRATION TIMING DIAGRAM
S0 S1 CLK S2 S3 S4 S5
WC32P020-XXM
A31-A0
D31-D0
FC2-FC0
SIZ1-SIZ0
ECS# 7 OCS#
AS#
DS#
R/W#
DBEN 16 DSACK0#
DSACK1# 33 BR# 35 34 BG# 39 37 BGACK# 39A
NOTE: Timing measurements are referenced to and from a low 0.8V and a high voltage of 2.0V, unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0.8V and 2.0V.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. December 2002 Rev. 2 12 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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FIGURE 9 114 PIN GRID ARRAY, PGA (P2)
34.55 (1.360) 0.50 (0.020) SQ.
WC32P020-XXM
4.64 (0.182) 0.32 (0.012) N M L K J H G F 0.49 (0.019) 0.06 (0.002) E D C B A 1 3.18 (0.125) 0.64 (0.025) 2 3 4 5 6 7
2.54 (0.100)
2.54 (0.100)
8
9
10 11 12 13
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
FIGURE 10 - 132 LEAD, CERAMIC QUAD FLAT PACK, CQFP (Q2)
27.43 (1.080) SQ 0.12 (0.005) 22.36 (0.880) 0.50 (0.020) SQ 4.13 (0.162) 0.19 (0.007)
Pin 1
20.32 (0.800) REF
27.43 (1.080) 0.12 (0.005)
4.13 (0.162) 0.19 (0.007)
0 - 8
0.76 (0.030) 0.12 (0.005) 0.64 (0.025) 0.13 (0.005) 0.64 (0.025) MIN
DETAIL A
0.64 (0.025) 0.25 (0.010) 0.04 (0.002)
DETAIL A
0.17 (0.006) 0.04 (0.001)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
White Electronic Designs Corp. reserves the right to change products or specifications without notice. December 2002 Rev. 2 13 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
ORDERING INFORMATION
WC32P020-XXM
W C 32 P020 - X X M
DEVICE GRADE: M = Military Temperature PACKAGE: Q2 = 132 Lead Ceramic Quad Flatpack, CQFP P2 = 114 Pin Ceramic PGA Operating Frequency in MHz 68020 32 bit Wide MICROCONTROLLER WHITE ELECTRONIC DESIGNS CORP. -55C to +125C
White Electronic Designs Corp. reserves the right to change products or specifications without notice. December 2002 Rev. 2 14 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com

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